DQPSK調(diào)制解調(diào)verilog代碼quartus_電路方案

名稱：DQPSK調(diào)制解調(diào)（代碼在文末付費下載）

語言：Verilog

要求：使用Verilog語言進行DQPSK調(diào)制和解調(diào)，并進行仿真

演示視頻：

部分代碼展示

//DPSK解調(diào)模塊
module?QPSK_demodu(
????input?clk,
????input?rst,
?input?[7:0]?qout,//調(diào)制波
?input?[7:0]?cos_wave,//本地載波
?input?[7:0]?sin_wave,//本地載波?
????output?[1:0]?data//解調(diào)輸出
);
wire?[16:0]?cos_mul;
wire?[16:0]?sin_mul;
assign?cos_mul=cos_wave*qout;//調(diào)制波形與本地載波相乘
assign?sin_mul=sin_wave*qout;//調(diào)制波形與本地載波相乘
reg?[5:0]filter_cos_cnt=0;//32
reg?[5:0]filter_sin_cnt=0;//32
reg?demodulate_a=0;
reg?demodulate_b=0;
//采用計數(shù)器濾波，檢測到cos_mul(15)?=?'1'后計數(shù)到25
always?@(posedge?clk)
??begin
????if(rst)
filter_cos_cnt<=6'd0;
?else
?if(cos_mul[15]==1)?
filter_cos_cnt<=6'd1;
????else?
???if(filter_cos_cnt==6'd0)
filter_cos_cnt<=6'd0;
else
if(filter_cos_cnt>=6'd25)
filter_cos_cnt<=6'd0;
else?
filter_cos_cnt<=filter_cos_cnt+6'd1;
??end
always?@(posedge?clk)
begin
??if(filter_cos_cnt==6'd0)
demodulate_a<=0;//濾波輸出解調(diào)的a路信號
??else
??????demodulate_a<=1;//濾波輸出解調(diào)的a路信號
end
//采用計數(shù)器濾波，檢測到sin_mul(15)?=?'1'后計數(shù)到25
always?@(posedge?clk)
??begin
????if(rst)
filter_sin_cnt<=6'd0;
?else
?if(sin_mul[15]==1)?
filter_sin_cnt<=6'd1;
????else?
???if(filter_sin_cnt==6'd0)
filter_sin_cnt<=6'd0;
else
if(filter_sin_cnt>=6'd25)
filter_sin_cnt<=6'd0;
else?
filter_sin_cnt<=filter_sin_cnt+6'd1;
??end
always?@(posedge?clk)
begin
??if(filter_sin_cnt==6'd0)
demodulate_b<=0;//濾波輸出解調(diào)的b路信號
??else
??????demodulate_b<=1;//濾波輸出解調(diào)的b路信號
end
//////////////
reg?[7:0]?cnt=8'd0;
always?@(posedge?clk)
??begin
????cnt<=cnt+1;
??end??
reg?a_buf=0;
reg?b_buf=0;
reg?a_buf2=0;
reg?b_buf2=0;
wire?D_a,D_b;
always@(posedge?clk)
if(cnt==8'd1)?begin
a_buf<=demodulate_a;
b_buf<=demodulate_b;
a_buf2<=a_buf;//a路延遲
b_buf2<=b_buf;//b路延遲
end
//差分解調(diào)
assign?D_a=a_buf?^?a_buf2;//Cn=Bn^Bn-1
assign?D_b=b_buf?^?b_buf2;//Cn=Bn^Bn-1
wire?[1:0]data_buf;
assign?data_buf={D_a,D_b};//輸出差分解調(diào)后的2bit數(shù)據(jù)
assign?data=data_buf;
endmodule

設(shè)計文檔(文檔點擊可下載)：

1. 工程文件